Physics 116B, Winter, 2011
Lecture: MWF 2:103:00 PM, Rm.185 Physics (in Physics atrium area, west side).
Lab: Monday (Sec. 2) or Wednesday (Sec. 1) 3:106 PM Rm. 152 Roessler.
Instructor: Prof. David E. Pellett, 337 Physics, (530) 7521783,
Office hours: typically either Tuesday 3:104 or Thursday 4:105 in 152 Roessler as announced in SmartSite or by appointment.
Email: pellett (at) physics (dot) ucdavis (dot) edu.
TA: Mark Triplett
Office hours: TBA
Email: mttriplett (at) ucdavis (dot) edu
Reader: Eric Warren Sangaline
Office hours: Thursdays 45 PM in Room 394 Physics
Email: ewsangaline (at) ucdavis (dot) edu
Last updated Thu, Mar 24, 2011
Prospectus
Physics 116B is an introduction to pulse response of circuits, digital electronics and computer fundamentals. It is valuable for students who want to do experimental work, who want to understand the basis of our increasingly electronic environment or who want to develop new instrumentation or technology.
The prerequisite is Physics 116A (or consent of instructor), which covers DC and steadystate AC circuit theory, semiconductor device fundamentals and analog circuits.
Here is the web page for Physics 116A from last quarter.
Physics 116B Winter 2011 Preliminary Outline (lab sequence may be modified)
Some notes will also be posted in the Lecture Notes folder of SmartSite Resources
Week 
Monday 
Topics/Notes 
Lab 
1 
Jan 3 
Class and lab start Mon., Jan. 3
First day lecture notes here
Intro.; comparator, Schmitt trigger
Pulse circuit analysis;
relaxation osc.
(Notes on BJT Schmitt trigger) 
10: Schmitt Trigger
LF411 Op Amp Specifications
(same pinout as 741) 
2 
Jan 10 
555 Timer
TLC555 Timer Notes (lab intro)
Laplace transform (table here)

11: Relaxation Oscillator and One Shot
Also: TLC555 timer specs
Alternate thermistor curve (no white dot) 
3 
Jan 17 
M. L. King holiday on Monday
Logic gates and Boolean algebra (notes)

(No labs this week due to Monday holiday) 
4 
Jan 24 
Combinational circuit design
Logic circuits: TTL, CMOS, ECL
Notes on logic circuits (Rev. 2/5/06)
RTL pulse response demo
25 Min. Quiz 1 Fri., Jan. 28 
12: Combinational Logic

5 
Jan. 31 
Flipflops and counters 
13: Inside Digital ICs

6 
Feb 7 
Logic Circuits II (Rev, 2/28/11)
Sequential circuits (notes on design)
Also refer to this note on timing and glitches 
14: Sequential Logic Datasheet for 74LS74A

7 
Feb 14 
A to D, D to A conversion.
Exam Friday, Feb. 18

15: A to D and D to A Conversion
datasheets for 74LS191, LM311,
DAC08 DAC (use P pkg)

8 
Feb 21 
Presidents' Day holiday on Monday
RAM, Data busses
Computer data representations
Microcomputer architecture 
W:16: Data Bus, TriState Outputs and Memory (new version for 2011)
Datasheets: 74LS241 and 8 kByte SRAM (Cypress CY7C185) 
9 
Feb 28 
Arduino prototyping platform
Atmel AVR Microcontroller

M: See previous week
W: Lab 17: Arduino introductory projects.
Review Arduino references in Assignment 7 before lab to the extent possible.

10 
Mar 7 
25 Min. Quiz 2 Mon., Mar. 7
AVR Assembly Language and I/O
Introduction to sampled signals (notes on SmartSite) 
M: See previous week
W: Lab 18, Atmel AVR assembly language and AT90S8515 microcontroller
Review references in Assignment 8 before lab. 
11 
Mar 14 
Last class Mon., March 14 
M: See previous week 


Final Exam on Fri., March 18,
8:00 AM  10:00 AM 

Texts:
Bobrow, Fundamentals of Electrical Engineering, 2nd ed.
Horowitz and Hill, The Art of Electronics, 2nd ed.
References:
Atmel Mega168 microcontroller and Arduino open source electronics prototyping platform
plus library references and supplementary handouts
Grading: 9% Quiz 1, 18% MT, 9% Quiz 2, 25% Lab (required, on time), 10% HW, 29% Final.
Assignments
Assignment, Week 1: Read Bobrow, Ch. 10: Sec. 10.5; Ch. 3 (RC charging and discharging, response of circuits to pulses, particularly secs. 3.3 and 3.4, integrator, differentiator); Ch. 7: 7.3 (BJT cutoff and saturation; emittercoupled Schmitt trigger; switching time – here are Notes on SPICE analysis of a BJT Schmitt trigger), 544546 (MOSFET as switch).
 For Lab, the Schmitt Trigger lab writeup has the following problem to work in your lab notebook: prove the equation for V_{th} in terms of V_{bb} and V_{out}. Hint: use the Thevenin equiv. of the voltage divider formed by V_{bb }, R_{1 }and R_{2}.
 Problems (due Wednesday, 1/12/11): 10.70, 10.71, 10.75(b,c), 10.77(a), 3.33.
 Notes: For 10.75, refer to Table 7.3 on p. 491 of Bobrow for the assumed values of V_{BE} and V_{CE} when an npn BJT is in saturation (ON) and for the maximum value of V_{BE} to remain in the cutoff state. "The low voltage" refers to v0 when Q1 is OFF and Q2 is ON.
For 3.33, find the Thevinen equivalent of the voltage source and 3 resistors driving the capacitor. Also, assume the voltages and currents have reached their steadystate values prior to t=0.
Assignment, Week 2: Read Lab 11 writeup before coming to class Monday. Read Bobrow, Ch. 5: 5.55.7 (Laplace transform circuit analysis). Notice that the Laplace transformation solutions are complete solutions to the circuit differential equations, including the effect of the initial conditions (zero or nonzero). Figures 5.38(c) and 5.39(c) show how to include nonzero initial conditions for inductors and capacitors, respectively.
 Problems (due Friday, 1/21/11): 3.9(e) (assume zero initial conditions), 5.59(c), 5.61(b), 5.68 (assume zero initial conditions), 5.76 (assume zero initial conditions).
 For the problems in Ch. 5, refer to the table of Laplace transforms linked in Week 2 of the class outline above (or here). In particular, note the Laplace transformation frequency domain relations for circuit elements (assuming zero initial conditions):
 Z_{R}(s) = R
 Z_{L}(s) = sL
 Z_{C}(s) = 1/(sC).
 These are the same relations we worked with last quarter when dealing with phasors with complex frequency s. This is discussed in the text in Sec. 5.7. Some of the problems also require use of the method of partial fractions, discussed in Sec. 5.6.
 We assume you have some familiarity with Laplace transforms from Math 22B. We will go over examples in class Wednesday.
 Optional further reading: you may be interested in the section, "Introduction to Communications," Sec. 10.6.
Assignment, Week 3: Read material in Bobrow on binary numbers, Boolean algebra and combinational logic circuits, namely Ch. 11 and Sec's 1 and 2 of Ch. 12 plus these notes on logic gates and Boolean algebra.
 Problems due Wed. 1/26/11: Use Laplace transform techniques to solve the following problems from Ch. 5: 5.77, 5.83 (find v(t) only), 5.86 (find i(t) only). Also
 Special Problem 1:
 Find the output v_{2}(t) for the high pass RC filter shown in Fig. 5.5 of Bobrow for a ramp input v_{1}(t) = α t u(t), where α is a constant.
Assume v_{1}=v_{2}=0 for t<0. Recall that ω_{C} = 1/RC.  Evaluate v_{2}(t) for ω_{C} = 10 000 rad/s and α = 10 V/s; sketch the output waveform.
 Why might you expect the output to be approx. constant if v_{2 }<<_{ }v_{1}? Find the output voltage for t >> RC (steady state output).
 Find the rise time of v_{2 }(time required to go from 10% to 90% of the steady state voltage).
Assignment 4:
 Read 7.47.6, 8.4 to get an overview of logic circuit families such as TTL, Schottky TTL, ECL and CMOS. We will discuss simplified models in class (notes here or in Week 4 of the Class Outline, above); 12.3 (flipflops and sequential circuit introduction – the first part of this section is needed for Lab 13.).
 Problems (due Wednesday, 2/2/11): Bobrow, 11.22, 11.24, 11.27, 11.34, 11.37, 11.45, 11.51(b): make a Karnaugh map, use it to express the function in simplified sumofproducts form and implement with two and threeinput NANDs and inverters; 11.53(c), 11.57(b): also implement with two and threeinput NANDs and inverters.
Assignment 5:
 Read Bobrow, Sections 13.1  13.3 and the notes on Sequential Circuit Design from Week 6 of the course outline (above).
 Further reading: Bobrow, 13.4 (the section on DACs and ADCs is needed for the ADC lab next week).
 The text by Horowitz and Hill (H&H) has more detailed information and valuable lore about the material we are covering and includes an introduction to some needed additional topics such as programmable logic devices (PLDs). A guide to relevant material is as follows:
 H&H Sec. 8.158.29, 8.338.35: logic and sequential circuit design including basic PLD applications; logic circuit pathologies.
 H&H Ch. 9 through Sec. 9.14: logic families, interconnections, do's and don'ts.
 H&H Sec. 9.159.25: ADC's and DAC's. Fig. 9.47 shows a basic DAC similar to the one used in Exp't 15.
 H&H will be the primary text when we talk about microcomputers.
 Problems (due Friday, 2/11/11): Bobrow, 12.16(b), 12.19, 12.34, 12.37(also make a state diagram), 13.12(a). (One or two more may be added.)
Assignment 6:
 Reading: continue with the extensive reading material in Assignment 5.
 Problems (due Wednesday, 2/16/11): this set of 4 problems.
 Note on Assignment 6:
 (a) Maximum Clock Frequency: the maximum clock frequency (inverse of minimum clock period) for a synchronous sequential circuit was discussed in class. The minimum clock period is the sum of
 the flipflop delay (assuming all ff's are the same)
 plus the sum of the gate delays in the longest path from a flipflop output to a flipflop input (with external inputs to the circuit itself held constant)
 plus the flipflop setup time.
 Use worst case values.
 (b) Setup and Hold times: the flipflop inputs of a synchronous sequential circuit must be held constant during the flipflop setup and hold times. Failure to do this can lead to an unexpected transition or to a metastable state (see Horowitz and Hill, pp. 510511, 552.)
 (c) Asynchronous inputs: an asynchronous external input signal is one which can occur at a random time not synchronized with the system clock. It could change state during the times the inputs are supposed to be steady. An asynchronous signal can be synchronized with the system clock by putting it through one or two stages of D flipflops with clock inputs connected to the system clock before connecting it to the circuit. This way the sequence of the main counter is protected from malfunction due to the asynchronous nature of the external signal.
 (d) Glitches: a glitch is an undesired short signal arising in an electronic circuit. A glitch can occur if logic (such as an AND) can produce a valid output momentarily as inputs change from one state to another even if the state detected is not the initial or final state. For example, consider F=BA, the AND of A and B corresponding to a two bit binary number from a binary counter circuit (A being the less significant bit). F would be 1 in the state B=1, A=1 ("3") and could be used to detect ("decode") this state. BA could also be 1 for a short time as the counter made the transition from "1" (01) to "2" (10) if A stayed high for a brief time after B changed to 1. If you were trying to detect state "3" to reset the counter (to count modulo 3, for example), it could be reset prematurely by the glitch. Since the glitch is short, it might cause the reset only intermittently. Also, since the pulse is short, it may be hard to see on an oscilloscope. Not all transitions generate glitches. For example, in going from "0" to "1," only one input changes, so there would be no glitch on F for that transition. See figure:
^{Assignment 7:}
 Problems due Friday, March 4, 2011: This set of 6 problems.
 Continue reading the material in Horowitz and Hill from Assignment 5 on programable logical devices (PLDs). In Chapter 8, there are examples of implementing a simple combinational circuit and a finite state machine with a PLD using a hardware description language called CUPL. Wikipedia has a good overview and an introduction to hardware description languages such as VHDL. Many specialized digital applications are implemented with complex PLDs known as FPGAs. One common use in experimental particle physics is for testing individual modules used for tracking particles. If you would like to learn more about using PLDs, a good place to start is Digital Design: Principles and Practices by Wakerly.
 Microcomputers, microprocessors and microcontrollers
 In the remainder of this course, we will emphasize Atmel AVR microcontrollers and the Arduino prototyping platform. Many of the microcontroller concepts are similar to those described for the Motorola 68000 processor in Horowitz and Hill. But the Atmel microcontroller is an "all in one" device with AVR processor, EEPROM, SRAM and Flash RAM, timer/counters, analog and digital I/O pins and a builtin ADC in advanced models.
 We will begin with the Arduino, based on the Atmel Mega168 microcontroller, to get a feeling of what the system can do from a highlevel perspective. This will be the subject of Lab 17.
 Then we will look at the AVR microcontroller structure using as an example the simpler AT90S85815. In Lab 18, we will experiment with AVR assembly language using the AVR Studio development system. Also, we will examine a more advanced Arduino application developed by UC Davis Physics alumnus Dr. Mike Madison. This digitizes and plays back signals at a 62.5 kHz sampling frequency.
 Specific general topics:
 Binary Arithmetic, Hexadecimal Notation, 2's Complement Negative Numbers Review  Bobrow, Secs. 11.1, 11.2 and Horowitz and Hill, Sec. 10.23; ASCII Code  Horowitz and Hill, Sec. 10.19 (pp. 720722).
 Programming and operating system concepts: Horowitz and Hill, Secs. 10.1710.18.
 Microprocessor overview with Motorola 68000 processor and instruction set: Horowitz and Hill, Ch. 11, pp. 743752 (once over lightly).
 The M68000 processor architecture and instruction set provide a good basis for an introduction to microcomputer concepts. It was used for early graphical user interface (GUI) computer systems from Sun, Apple, HP, Commodore Amiga and Atari as well as for data acquisition and process control applications (e.g., VME bus systems). It has been used in game systems (e.g., Atari "Marble Madness" arcade game, Sega Genesis), Palm PDAs and TI calculators as well. It is an example of a complex instruction set computer (CISC) as opposed to a reduced instruction set computer (RISC) such as the Atmel AVR.
 Read the material on Arduino programming as indicated in the Lab 17 writeup. Here are the appropriate web links:
^{Assignment 8:}
 Problems: AVR Review Exercises for Assignment 8 on SmartSite (not to be turned in). The solutions are there too.
 Reading:
 Atmel AVR processor overview. Although the last two labs use the Arduino system with its Atmel Mega168 microcontroller, we will study the AVR architecture and instruction set with a simpler version, the AT90S8515.
 As stated above, we will experiment with AVR assembly language using the AVR Studio development system in Lab 18.
 In class, we will discuss sampled waveforms, the sampling theorem, the Nyquist critical frequency and aliasing. Also, we will examine a more advanced Arduino application developed by UC Davis Physics alumnus Dr. Mike Madison. This digitizes and plays back signals at a 62.5 kHz sampling frequency. It uses assembly code to address Mega168 microcontroller registers and an interupt service routine in an Arduino program. Slides will be posted in SmartSite. The sampling theorem and aliasing (to be covered in 116C), interrupts and the Madison Arduino application will not be on the final exam.
Announcements
Please refer to the SmartSite announcement area
2011: Preliminary Topic Timeline
For Quizzes, Midterm exam and Final, including Labs
(Under development. See also the course outline table above)
 Analog meets digital I: comparator, Schmitt trigger, relaxation oscillator, 555 timer
 BJTs in cutoff and saturation; MOSFETs as switches
 Emittercoupled Schmitt trigger
 Simulation with SPICE
 Pulse circuit analysis: differential equations and Laplace transforms, H(s) again for L, R, C
 Laplace transform solutions with nonzero initial conditions
 RC networks, integrators, differentiators
Quiz 1 to cover material up to this point.
 Combinational circuits: logic gates, Boolean algebra, Karnaugh maps, minterms
 Implementation with SSI circuits
 Tristate outputs, open collector outputs
 Simulation with diglog
 MSI multiplexers, encoders, decoders, adders, ROM, PLA, etc.
 Use for implementing logical functions
 binary numbers, hexadecimal numbers, Gray code
 Logic families: TTL, LSTTL, CMOS, ECL logic circuits, pulse response speed, Schottky diodes and transistors, new directions
 Flipflops (RS latch, clock, D, T, JK; edge triggering)
 Sequential circuits: asynchronous vs. synchronous circuits
 State tables, state diagrams, transition maps, etc.
 Shift registers, counters
 Design and implementation with flipflops and gates
 isolated states, selfstarting counters
 Asynchronous inputs and how to deal with them
 Decoding glitches
 Maximum clock frequency
Midterm exam to cover material up to this point.
 MSI counters (binary, BCD, up/down, preset input, count enable input, carry output, connecting together to get more bits, altered sequences, etc.)
 VLSI memory chips (static RAM, dynamic RAM, EEPROM and flash memory)
 Synchronous state machines in general, PLA, FPGA overall concepts (H&H, other reading assignments; Bobrow refers to "FPLA")
 Analog meets digital II: DACs, ADCs
 Data/Address/Control bus and tristate outputs; memory R/W access (as in Lab 16)
Quiz 2 to cover material up to this point, emphasizing recent topics. (The quiz may have questions on logic families and circuitry, interconnection dos and don'ts and other material covered in the H&H reading assignments and/or mentioned in class.)
 Basic microcomputer concepts:
 ASCII code, hexadecimal numbers, twos complement integers
 Chip interconnection and I/O signals (general overview)
 Computer registers and instructions
 Assembly language
 I/O and software code
 Interrupts (see H&H pp. 756758, 778779 for example)
 Sampled waveforms, Nyquist critical frequency, aliasing, dynamic range
 sample and hold circuit;
 requirement for antialiasing low pass filter in general.
 Atmel AVR microcontroller and Arduino
 General concepts: "all in one" device with RISC processor, EEPROM, SRAM and Flash RAM, ADC, timer/counters, analog and digital I/O pins
 AVR architecture and assembly language
 Atmel development tools: assembler, debugger
 Arduino board with USB interface: experience with development tools and Arduino language based on C
 This slide about the final exam was presented in class Monday, 4/14.
Final Exam will be comprehensive but will have some emphasis on recent material. Note: the sampling theorem and aliasing (to be covered in 116C), interrupts and the Madison Arduino application will not be on the final exam.
Links to topics relevant to class/lab
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